1. Field of the Invention
This invention is related to the field of electronic circuit simulation.
2. Description of the Related Art
Circuit simulation tools provide a way for the circuit designer to simulate the behavior of a complex design, identify any problems, and make alterations and enhancements to the circuit before arriving at a final design. That iterative design process has in turn improved the reliability of the end products that incorporate a given circuit design. One of the most popular circuit simulation tools is the Simulation Program with Integrated Circuit Emphasis (or SPICE). Many commercial versions of SPICE are available. In addition to SPICE-like simulators, functional simulators (which primarily are used to verify logical function of circuits) are often used, such as high level description language (HDL) simulators. HDL simulators include both event-driven simulators and cycle-based simulators.
While considered highly accurate, traditional SPICE is typically too slow for the analysis of large circuits, as the single design matrix that SPICE uses to solve the system of equations describing the circuit can grow quadratically with the number of circuit elements. To work around this limitation, so called “Fast-Spice” simulators in part achieve greater speed by intelligently partitioning a single design matrix into many smaller matrices. These small partition matrices are solved independently, and their solutions combined to form an overall solution. Design partitioning is often based on either channel-connected components or user-defined design hierarchy. A channel-connected component consists of non-linear elements which are graph-connected through their channel terminals, along with graph-connected linear elements.
A modern silicon chip may contain millions of gates, flip-flops, registers, and cells. Many of these design primitives are electrically identical or nearly so—that is, they have the same transistor configurations and sizing and are driving an equivalent (or nearly equivalent) load. For example, a design may contain thousands of identical NAND gates all driving a capacitive load of between 1.2 and 1.4 femto-Farads (fF).
Often, these electrically equivalent entities see the same input transitions—a rising or falling edge of the same shape, direction, and duration—at the same time. This is referred to as “spatial repetition,” as two different instances of an electrically equivalent entity that are separated by space undergo identical state transitions. The phenomenon of spatial repetition is particularly common in N-bit wide logic, where adjacent electrical partitions see identical transitions from the prior stage data-path logic. Further, over the course of a long transient simulation, partitions will often see the same input stimulus transitions many times. This is referred to as “temporal repetition” or repetition across time. A partition may generally refer to any portion of an overall circuit design.
In the prior art, it has been impossible (or at least impractical) to fully exploit spatial and temporal repetition in a simulation. By attempting to match only against states derived from the same hierarchical definition (e.g. the Tcherniaev method described below), the opportunity to match partitions from different definitions which are exactly or nearly equivalent is lost. Further, attempting to match a transient partition state against all other partition states in the design is too time-consuming. The probability that all internal state variables (node voltages, capacitor charges, inductor currents, etc.) will match between two arbitrary partitions at an arbitrary point in time is typically too low to make that search worthwhile.
Traditional SPICE takes no advantage of either spatial or temporal repetition in simulation. Instead, the entire design is simulated simultaneously in a single monolithic matrix. U.S. Pat. No. 6,577,992 by A. Tcherniaev, et. al. takes advantage of the spatial repetition inherent in hierarchical microelectronic circuit design. In the Tcherniaev mechanism, the user-defined hierarchical structure limits the matching to only those circuits having identical hierarchy. This precludes matching, for example, two NAND gates which are in entirely different subcircuits, but are loaded similarly (or are structurally different, but behave similarly from a functional standpoint). Furthermore, the Tcherniaev method compares the dynamic voltage state of a particular instance to all other dynamic voltage states associated with the corresponding subcircuit definition for isomorphism. Since the number of potential dynamic voltage states is essentially infinite, the probability that two states match at an arbitrary point during transient simulation is low. U.S. Patent Application Publication 2005/0149312 describes another mechanism that relies on hierarchy.